Speed measurement for a bank of motors

Project Description

The Problem
A petro-chemical company for a new process wanted to measure speeds and acceleration of high speed motors setup as banks of eight each. The proximity sensors gave out a high speed pulse train for each of these eight motors in the bank. The high resolution requirement coupled with fast periodic measurement was a challenging problem. 

The Solution

The resolution on speed was 0.01% and that on acceleration was 0.001%. These parameters had to be measured and be available for scanning by an external remote controller once every second. The resolution had to be maintained at both the low end and the high end of the speed spectrum, thus greatly increasing the dynamic measurement range.

The entire electronics and firmware was designed to meet these specifications. A Xilinx FPGA was chosen to dynamically pre-scale the pulse train based on the current speeds. The pulse widths were then measured with a high speed clock to allow for the required resolution at all the speed ranges. The FPGA was designed to measure the speed of all the eight motors concurrently. The system was designed to complete all the measurements once in 500 milliseconds. The results were then transferred to a sixteen bit micro-controller. A remote controller system would query this unit through the Ethernet interface once very second for both speed and acceleration data for all the eight motors. The microcontroller implemented the communication protocol to this remote system. A Modbus protocol was also implemented to enable PLCs or SCADA systems to query the speed and acceleration for all the eight motors at regular intervals. A local LCD panel displayed the measurements which was updated every second.

The electronics was designed to run in a high electrical noise environment. The input signals from the eight channels went through signal conditioning stages followed by an anti-aliasing Nyquist filter. Isolated power supplies, communication channels and sufficient voltage margins enabled the board to run effectively in an electrically hostile environment. A watch dog timer ensured that any processor or FPGA lock up would trigger an immediate reset.

Digital Filter algorithms were designed and implemented to reduce noise. A digital notch filter helped to minimize noise induced from two different frequencies present in the environment. This was followed by a moving average filter with threshold algorithm implementation that eliminated most of the white noise without sacrificing the response time for a step change.

The result was a low cost electronics board with firmware that met all the requirements and enabled the client to implement the new process.

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